Fosbury-flop - translation to russian
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Fosbury-flop - translation to russian

HIGH JUMP STYLE
Fosbury Flop; Fozberry flop; The Fosbury Flop

Fosbury-flop      

['fɔzb(ə)riflɔp]

существительное

спорт

«фосбери-флоп» (вид прыжка в высоту)

set-reset flip-flop         
  • serial-in, parallel-out (SIPO) shift register]]
  • D flip-flop symbol
  • An implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock
  • Circuit symbol of a dual-edge-triggered D flip-flop
  • An implementation of a dual-edge-triggered D flip-flop
  • A dual-edge triggered D flip-flop implemented using XOR gates, and no multiplexer.
  • Schematics from the Eccles and Jordan trigger relay patent filed 1918, one drawn as a cascade of amplifiers with a positive feedback path, and the other as a symmetric cross-coupled pair
  • Flip-flop setup, hold and clock-to-output timing parameters
  • Symbol for a gated SR latch
  • SR}} NAND latch
  • A circuit symbol for a positive-edge-triggered JK flip-flop
  • JK flip-flop timing diagram
  • NAND Gated SR Latch (Clocked SR flip-flop). Note the inverted inputs.
  • A master–slave D flip-flop. It responds on the falling edge of the ''enable'' input (usually a clock)
  • An animation of a SR latch, constructed from a pair of cross-coupled [[NOR gate]]s. Red and black mean logical '1' and '0', respectively.
  • An SR AND-OR latch. Light green means logical '1' and dark green means logical '0'. The latch is currently in hold mode (no change).
  •  4=S = 1, R = 1: Not allowed
}}
Transitioning from the restricted combination (D) to (A) leads to an unstable state.
  • NOR]] gates (on right).
  • SR}} latch constructed from cross-coupled [[NAND gates]].
  • How an SR NOR latch works.
  • A circuit symbol for a T-type flip-flop
  • A transparent latch circuit based on [[bipolar junction transistor]]s
  • Symbol for a gated D latch
  • A CMOS IC implementation of a dynamic edge-triggered flip-flop with reset
CIRCUIT THAT HAS TWO STABLE STATES AND CAN BE USED TO STORE STATE INFORMATION
Transparent latch; Setup time; JK flip-flop; JK flip flop; Flip flop (electronics); Jk flipflop; T flipflop; Sr flipflop; D flipflop; Flipflop (switch); Sr latch; Latch (electronics); Bistable circuit; Gated latch; Gated D latch; Latch (electronic); SR latch; Flip flop circuit; SR flip-flop; J-k ff; SR Flip Flop; SR Latch; T flip flop; T flip flops; T flip-flops; T flip-flop; JK flip-flops; JK flip flops; D flip-flop; D flip flop; D flip-flops; D flip flops; Sr flip-flop; SR flip-flops; SR flip flops; Set-Reset flip flop; Set-Reset flip flops; Set-Reset flip-flops; Set-Reset flip-flop; Set-Reset latch; Set-Reset latches; SR latches; RS latch; JKFF; SR flip-flop circuit; Flip-flop-flap; Setup Time; D latch; D Latch; Jk ff; Bistable flip-flop; Polarity hold latch; Flip-flop element; R-S latch; SR Latches; Earle latch; Edge-triggered flip-flop; D flip-flip; JK bistable; Digital reset (electronics); Digitally set (electronics); Digital set (electronics); Digitally reset (electronics); Digital set (logic state); Digital reset (logic state); D-type flip-flop

общая лексика

триггер с раздельным входом

setup time         
  • serial-in, parallel-out (SIPO) shift register]]
  • D flip-flop symbol
  • An implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock
  • Circuit symbol of a dual-edge-triggered D flip-flop
  • An implementation of a dual-edge-triggered D flip-flop
  • A dual-edge triggered D flip-flop implemented using XOR gates, and no multiplexer.
  • Schematics from the Eccles and Jordan trigger relay patent filed 1918, one drawn as a cascade of amplifiers with a positive feedback path, and the other as a symmetric cross-coupled pair
  • Flip-flop setup, hold and clock-to-output timing parameters
  • Symbol for a gated SR latch
  • SR}} NAND latch
  • A circuit symbol for a positive-edge-triggered JK flip-flop
  • JK flip-flop timing diagram
  • NAND Gated SR Latch (Clocked SR flip-flop). Note the inverted inputs.
  • A master–slave D flip-flop. It responds on the falling edge of the ''enable'' input (usually a clock)
  • An animation of a SR latch, constructed from a pair of cross-coupled [[NOR gate]]s. Red and black mean logical '1' and '0', respectively.
  • An SR AND-OR latch. Light green means logical '1' and dark green means logical '0'. The latch is currently in hold mode (no change).
  •  4=S = 1, R = 1: Not allowed
}}
Transitioning from the restricted combination (D) to (A) leads to an unstable state.
  • NOR]] gates (on right).
  • SR}} latch constructed from cross-coupled [[NAND gates]].
  • How an SR NOR latch works.
  • A circuit symbol for a T-type flip-flop
  • A transparent latch circuit based on [[bipolar junction transistor]]s
  • Symbol for a gated D latch
  • A CMOS IC implementation of a dynamic edge-triggered flip-flop with reset
CIRCUIT THAT HAS TWO STABLE STATES AND CAN BE USED TO STORE STATE INFORMATION
Transparent latch; Setup time; JK flip-flop; JK flip flop; Flip flop (electronics); Jk flipflop; T flipflop; Sr flipflop; D flipflop; Flipflop (switch); Sr latch; Latch (electronics); Bistable circuit; Gated latch; Gated D latch; Latch (electronic); SR latch; Flip flop circuit; SR flip-flop; J-k ff; SR Flip Flop; SR Latch; T flip flop; T flip flops; T flip-flops; T flip-flop; JK flip-flops; JK flip flops; D flip-flop; D flip flop; D flip-flops; D flip flops; Sr flip-flop; SR flip-flops; SR flip flops; Set-Reset flip flop; Set-Reset flip flops; Set-Reset flip-flops; Set-Reset flip-flop; Set-Reset latch; Set-Reset latches; SR latches; RS latch; JKFF; SR flip-flop circuit; Flip-flop-flap; Setup Time; D latch; D Latch; Jk ff; Bistable flip-flop; Polarity hold latch; Flip-flop element; R-S latch; SR Latches; Earle latch; Edge-triggered flip-flop; D flip-flip; JK bistable; Digital reset (electronics); Digitally set (electronics); Digital set (electronics); Digitally reset (electronics); Digital set (logic state); Digital reset (logic state); D-type flip-flop

общая лексика

время установления

нефтегазовая промышленность

время схватывания (цементного раствора)

время монтажа (буровой установки)

Definition

JK flip-flop
<hardware> An edge triggered SR flip-flop with extra logic such that only one of the R and S inputs is enabled at any time. This prevents a race condition which can occur when both inputs of an RS flip-flop are active at the same time. In a JK flip-flop the R and S inputs are renamed J and K. The set input (J) is only enabled when the flip-flop is reset and K when it is set. If both J and K inputs are held active then the outputs will change ("togle") on each falling edge of the clock. JK flip-flops can be used to build a binary counter with a reset input. http://play-hookey.com/digital/logic7.html. [Was it named after Jack Kilby?] (2004-07-17)

Wikipedia

Fosbury flop

The Fosbury flop is a jumping style used in the track and field sport of high jump. It was popularized and perfected by American athlete Dick Fosbury, whose gold medal in the 1968 Summer Olympics in Mexico City brought it to the world's attention. The flop became the dominant style of the event; before Fosbury, most elite jumpers used the straddle technique, Western Roll, Eastern cut-off or scissors jump to clear the bar. Though the backwards flop technique had been known for years before Fosbury, landing surfaces had been sandpits or low piles of matting and high jumpers had to land on their feet or at least land carefully to prevent injury. With the advent of deep foam matting, high jumpers were able to be more adventurous in their landing styles and hence experiment with styles of jumping.

Examples of use of Fosbury-flop
1. Her highly individual style – a cross between the western roll and the much later Fosbury flop – meant she went over the bar head first and so, the judges said, constituted an illegal dive.
What is the Russian for Fosbury-flop? Translation of &#39Fosbury-flop&#39 to Russian